The present invention relates to a circuit able to generate periodic signals such as clock signals. More particularly, the present invention relates to an improved delay locked loop circuit.
Many high speed electronic systems possess critical timing characteristics, which dictate the need to generate a periodic clock wave form so as to establish a precise time relationship with respect to one or more reference signals.
In fact the clock signal may need to be adjusted to stay in sync with the reference signal.
Usually, a phase locked loop circuit (PLL), which employs a voltage control oscillator (VCO), is used to provide the desired clock signal.
However, the VCO circuit based on PLL circuits shows some problems, such as the fake convergence, the stability and the need of a specific technology to implement the circuit.
Moreover, a PLL circuit is scalable with difficulty.
Moreover, in order to achieve the desired time relationship, the acquisition of information requires multiple iterations of signal through the PLL circuit, so as the time required can drive the VCO circuit to the correct frequency.
An alternative PLL circuit is the delay locked loop circuit (DLL) which generates a plurality of output signals with a predetermined delay with respect to an input reference signal.
In fact a PLL circuit changes the generated clock by adjusting a voltage input to the VCO circuit, whereas the DLL circuit adjusts the generated clock by adjusting a bias voltage to a series of buffers (in the case of a DLL circuit implemented in analog technology).
The DLL circuits are routinely employed in high speed phase alignment circuits, such as in Synchronous Dynamic Random Access Memories (SDRAM) and in microprocessors. Especially, due to their intrinsic simply design and stability, a DLL circuit is employed in all the applications where no clock synthesis is required.
Moreover, the DLL circuit is employed in circuits such as a serializer/deserializer, wherein the phase signals have to be equally spaced in time domain.
The general method that makes signals equally spaced in the time domain is to tap a chain of delay elements, wherein the delay time is controlled by a DLL circuit. Therefore, the DLL circuit obtains N equispaced phases (within a round angle) out of the input clock.
FIG. 1 shows a conventional DLL circuit.
A master clock signal MCLK 1 is input both a phase frequency detector (PFD) 2 and to a delay line 3. The delay line 3 can be implemented as a series of cells (not shown in FIG. 1), called delay cells.
An output 4 of the delay line 3 is input to the same PFD 2. A control logic 5 selects which tap out xcfx861-xcfx86n is propagated to the output.
The phase difference between the phase of the signal 4 and the phase of the MCLK 1, gives an indication of a phase error xcex5 to the control logic 5.
The control logic 5 responds to this phase error xcex5, counting upwards when the output 4 of the delay line 3 changes before the master clock signal MCLK 1, or counting downward when the output 4 of the delay line 3 changes after said master clock signal MCLK 1.
FIG. 2 shows outputs of the tap number zero, indicated as xe2x80x9ct0xe2x80x9d, and one, indicated as xe2x80x9ct1xe2x80x9d, along side the master clock MCLK 1.
As shown in such a FIG. 2, the two taps xe2x80x9ct0xe2x80x9d and xe2x80x9ct1xe2x80x9d are equally-spaced to each other by xcfx84 seconds.
Many factors may affect the number of clock cycles and the equispacing among the taps, such as the operating temperature, the process of implementing of the DLL circuit, especially the implementation of a delay cell, and the operating voltage of the DLL circuit.
As FIG. 3 shows, the clock signals 9, 10 and 11 output from taps 4 on the delay line 3 and they tend to jitter, that is they tend to vary in the time domain.
The rising edge of the clock signal 10 or 11 or both, does not always follow the rising edge of the master clock signal MCLK 1 by a fixed delay.
Moreover, in a conventional DLL""s architecture, the phase of the signal 4 and the phase of the MCLK 1 are not always aligned for every condition of temperature, voltage supply and process.
Furthermore, in some cases of undesired transitions on the voltage supply, caused, for example, by an hot insertion of a printed circuit board, may occur a corruption of the values stored in the delay cells of the delay line 3, and in these cases, sometimes, there is a fake convergence.
In the case of a fake convergence, the control logic 5 may output a random value, and, therefore, the control logic 5 proceeds to count up or down based upon the phase error xcex5 corresponding to this random value.
In view of the state of the art described, it is an object of the present invention to solve the aforementioned problems, and particularly to guarantee the arrival at the correct convergence from whatever initial condition is set to the DLL circuit.
Another object of the present invention is to guarantee the DLL circuit stays in the condition of convergence whatever conditions are settled.
According to the present invention, such object is attained by a circuit for generating a digital output signal locked to a phase of an input signal, comprising a plurality of delay cells, a first register containing a first value, a phase detector and a control logic, characterized by comprising a plurality of flip-flop devices, wherein storing said first value, a second register containing a second value, a plurality of adder nodes adapted to sum in each of said delay cells said second value with the content of said selected flip-flop device, being said delay cells adapted to provide said digital output signal, said phase detector, receiving said input signal and said digital output signal, adapted to detect the phase difference between said input signal and said digital output signal, said control logic adapted to control said first and second value in function of said phase difference.
Thanks to the present invention it is possible to realize a DLL circuit able to solve the problem of the fake convergence.
Thanks to the present invention it is also possible to realize a DLL circuit easier with respect to the prior art.
Thanks to the present invention it is also possible to realize an updating technique of the DLL circuit taps without lock problems.